Fig. 1

Block diagram of multi-source RF pulse generator system

Fig. 2

Block diagram of RF hardware board structure

Fig. 3

Schematic diagram of the reconfigurable AXI DDS module structure

Fig. 4

Block diagram of the DDS custom IP core schematic

Fig. 5

Application processor software design flowchart

Fig. 6

Flowchart of upper computer software design for PC

Fig. 7

Home-made RF hardware board physical diagram

Table 1

1 GB Dual DDR3 SDRAM with 15 memory sub-test data patterns and sequential write stress test results

Table 2

Gigabit ethernet transmission rate test results

Table 3

Hardware resource consumption of four-channel RF pulse generator FPGAs

Fig. 8

(a) RF pulse waveform at 63.87 MHz with 401 mV peak-to-peak; (b) RF pulse waveform at 63.87 MHz with 205 mV peak-to-peak; (c) 4-channel fast frequency modulation from 1 MHz to 2 MHz; (d) 4-channel fast phase modulation from phase 0 to phase π; (e) Dual-channel RF hard pulse waveform at 63.88 MHz with 206 mV peak-to-peak; (f) Dual-channel 5-Sinc RF soft pulse at 63.88 MHz with 206 mV peak-to-peak waveforms

Fig. 9

(a) Spectrogram of an RF signal with an output frequency of 63.87 MHz and a spectral window of 2 MHz; (b) Spectrogram of an RF signal with an output frequency of 63.87 MHz and a spectral window of 220 kHz

Fig. 10

Upper GUI for hard pulse CPMG sequences

Fig. 11

MR echo signal map of a hard-pulsed CPMG sequence

Fig. 12

Comparison of actual data inversion results