便携式磁共振多源射频脉冲发生器设计

doi:10.11938/cjmr20243137

摘要/Abstract

摘要：

在磁共振成像（Magnetic Resonance Imaging，MRI）领域，多源发射技术能够改善射频磁场均匀性，提高MRI图像质量. 本文提出了一种基于Zynq 7000 SoC全可编程片上系统的便携式磁共振多源射频脉冲发生器的设计. 该设计包含具有脉冲序列参数完全开放的上位机软件，以及一个全数字化、集成度高、双信用卡大小的硬件电路板，从而并行输出多路波形、频率、相位和幅度独立可调节的射频脉冲信号. 利用硬件描述语言Verilog在现场可编程门阵列（Field Programmable Gate Array，FPGA）内部构建高级可扩展接口的直接数字频率合成器（Advanced eXtensible Interface Direct Digital Synthesizer，AXI DDS）和乘法器等硬件电路，实现产生多路射频脉冲信号及信号调制的功能. 实验结果证明，该设计能正确发射四路MRI射频脉冲信号，为便携式磁共振多源射频脉冲发生器的设计提供一种全数字化、可重构性强、结构紧凑的可行方案.

关键词: 磁共振, 多源射频脉冲发生器, 可重构性, 小型化

Abstract:

In the field of magnetic resonance imaging (MRI), multi-source emission can improve the uniformity of radio frequency (RF) magnetic field and the quality of MRI images. In this paper, we propose a portable MRI multi-source RF pulse generator design based on the Zynq 7000 SoC all programmable system-on-chip. The design consists of a host computer software with fully open pulse sequence parameters and a fully digitalized, highly integrated, dual credit card-sized hardware board, which outputs multiple RF pulse signals with independently adjustable waveform, frequency, phase, and amplitude in parallel. The hardware description language Verilog is used to build AXI DDS (advanced eXtensible interface direct digital synthesizer) and multiplier circuits inside the FPGA (field programmable gate array) to realize the functions of generating multiple RF pulse signals and signal modulation. The experimental results show that the design can correctly transmit four MRI RF pulse signals, providing a fully digital, reconfigurable, compact, and feasible solution for developing a portable magnetic resonance multi-source RF pulse generator.

Key words: magnetic resonance, multi-source RF pulse generator, reconfigurability, miniaturization

中图分类号:

O482.53

刘颖, 袁斌华, 章浩伟. 便携式磁共振多源射频脉冲发生器设计[J]. 波谱学杂志, 2025, 42(3): 285-298.

LIU Ying, YUAN Binhua, ZHANG Haowei. Design of a Portable Magnetic Resonance Multi-source RF Pulse Generator[J]. Chinese Journal of Magnetic Resonance, 2025, 42(3): 285-298.

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子测试	数据模式描述	耗时/s
Memtest_0 (0)	递增模式, 写入每个内存地址的唯一值（数据 = 地址）	35.6024
Memtest_s (1)	写入0x00000000	22.9253
Memtest_s (2)	写入0xFFFFFFFF	22.9270
Memtest_s (3)	写入0xAAAAAAAA	22.9270
Memtest_s (4)	写入0x55555555	22.9253
Memtest_s (5)	交替写入0x00000000和0xFFFFFFFF	22.9270
Memtest_s (6)	交替写入0xFFFFFFFF和0x00000000	22.9270
Memtest_s (7)	交替写入0x55555555和0xAAAAAAAA	22.9270
Memtest_s (8)	交替写入0xAAAAAAAA和0x55555555	22.9253
Memtest_p (9)	干扰模式: 8 bits中每bit相同且每bit干扰一次	35.0279
Memtest_p (10)	干扰模式: 8 bits中每bit反转且每bit干扰一次	35.0385
Memtest_l (11)	具有不同种子的伪随机模式	36.6623
Memtest_l (12)	具有不同种子的伪随机模式	36.6623
Memtest_l (13)	具有不同种子的伪随机模式	36.6623
Memtest_l (14)	具有不同种子的伪随机模式	36.6623

时间间隔/s	传输数据量/(MB)	带宽/(Mb/s)
0.0~5.0	540	905
5.0~10.0	518	869
10.0~15.0	512	860
15.0~20.0	519	871
20.0~25.0	516	866
25.0~30.0	506	849
0.0~30.0	3111	870

资源	消耗资源数量	可用资源总数	使用率/%
LUT	4872	53200	9.16
LUTRAM	382	17400	2.20
FF	6370	106400	5.99
BRAM	13.5	140	9.64
IO	66	125	52.8
BUFG	1	32	3.13